This application claims the benefit of Korean Patent Application No. 1999-59464, filed on Dec. 20, 1999, which is hereby incorporated by reference for all purposes as if fully set forth herein.
1. Field of the Invention
The present invention relates to thin film transistors (TFT) of the type used in liquid crystal display (LCD) devices. More particularly, it relates to the insulation layers of such TFTs.
2. Discussion of the Related Art
A liquid crystal display (LCD) device uses the optical anisotropy and polarization properties of liquid crystal molecules to produce a predetermined image. Liquid crystal molecules have a definite orientation that results from their peculiar characteristics. The specific orientation can be modified by an electric field that is applied across the liquid crystal molecules. In other words, electric fields applied across the liquid crystal molecules can change the orientation of the liquid crystal molecules. Due to optical anisotropy, incident light is refracted according to the orientation of the liquid crystal molecules.
In general, liquid crystal display (LCD) devices use thin film transistors (TFTs) as switching elements that control the electric fields applied across the liquid crystal molecules.
An active matrix LCD (AM-LCD) incorporates a matrix of thin film transistors (TFTs) and pixel electrodes. Active matrix LCD (AM-LCD) are beneficial in that they can have high resolution and can be superior to alternative types when displaying moving images.
FIG. 1 is a cross-sectional view illustrating a conventional active matrix liquid crystal display (LCD) panel. As shown in FIG. 1, the LCD panel 20 has a lower substrate 2, an upper substrate 4, and an interposed liquid crystal layer 10. The lower substrate 2, which is referred to as an array substrate, has a TFT xe2x80x9cSxe2x80x9d that acts as a switching element to change the orientation of the liquid crystal molecules in the liquid crystal layer 10. As shown, the TFT xe2x80x9cSxe2x80x9d contacts a pixel electrode 14. The upper substrate 4 includes a color filter 8 that produces a color pixel image, and a common electrode 12 on the color filter 8. The common electrode 12 serves as a corresponding electrode for the pixel electrode 14. Together, voltages applied to those electrodes produce an electric field across the liquid crystal layer 10. The pixel electrode 14 is arranged over a pixel region, i.e., a display area. Furthermore, to prevent leakage of the liquid crystal layer, interposed between the substrates 2 and 4 is a sealant 6.
The principle of operating the AM-LCD device will now be explained. When a gate electrode 30 receives a gate signal that causes the TFT to turn ON, the data signals on a data line are applied to the pixel electrode 14. This induces an electric field across the liquid crystal molecules and causes those molecules to attain an orientation that depends on the data signals. On the other hand, when the gate electrode 30 receives a gate signal that causes the TFT to turn OFF, data signals are not applied to the pixel electrode 14. This removes the electric field and causes the liquid crystal molecules to attain a xe2x80x9crelaxedxe2x80x9d orientation.
In general, the manufacturing process for an active matrix liquid crystal display (LCD) panel depends on the materials used and on the design goal. For example, the resistivity of the materials used for the gate and data lines are important factors in the picture quality of large (say over 18 inch) LCD panels and of high resolution (for example SXGA or UXGA) LCD panels. With such LCD panels it is beneficial to use Aluminum (Al) or an Al-alloy for the gate lines and data lines.
LCD devices usually use inverted staggered type TFTs because such TFTs have a relatively simple structure and a superior efficiency. Inverted staggered type TFTs can be classified as either back channel etched (EB) or etch stopped (ES), depending on the fabrication method used. The manufacturing method of a back channel etched type TFT will now be explained.
FIG. 2 is a cross-sectional view of a back channel etched type TFT xe2x80x9cSxe2x80x9d as used in a conventional LCD device. As shown in FIG. 2, the TFT xe2x80x9cSxe2x80x9d includes: a substrate 1; a gate electrode 30 on the substrate 1; a gate insulation layer 32 over the substrate and over the gate electrode 30; an active layer 34 on the gate insulation layer 32; a source electrode 38 and a drain electrode 40 that are spaced apart from each other and that overlap sides of the active layer 34; and an ohmic contact layer 36 that is disposed between the active layer 34 and the source and drain electrodes 38 and 40.
The gate insulation layer 32 can be formed at relatively low temperature (below 350xc2x0). A material having superior insulation properties, such as Silicon Nitride (SiNx) or Silicon Oxide (SiO2), is beneficially used for the gate insulation layer 32. Moreover, pure amorphous silicon (a-Si:H) is beneficially used to form the active layer 34. Such silicon can also be formed at the relatively low temperatures used to form the gate insulation layer 32. After forming the active layer, the ohmic contact layer 36 is formed using a doped amorphous silicon (such as n+ a-Si:H). To dope the amorphous silicon, a doping gas having Boron or Phosphorous can be used. In a conventional LCD device, Phosphine (PH3), which includes Phosphorous, is generally used. The source and drain electrodes 38 and 40 are beneficially comprised of Chrome or Molybdenum.
FIG. 3 is a flow-chart illustrating the manufacturing process steps of the conventional TFT illustrated in FIG. 2.
In the first step, ST200, a glass substrate is provided and cleaned. That cleaning removes debris particles, organic materials, and other alien substances from the substrate. This reduces defects and enhances the overall properties of the resulting TFT. Furthermore, it improves adhesion between the substrate and subsequent layers, include a subsequent metal layer.
In the second step, ST210, a metal such as Aluminum or Molybdenum is deposited. Then, using a lithography process the gate electrode and a first capacitor electrode, which are portions of a gate line, are formed.
In the third step, ST220, the gate insulation layer and the semiconductor layers (the active layer and the ohmic contact layer) are sequentially formed. The gate insulation layer is beneficially comprised of Silicon Oxide or Silicon Nitride, and has a thickness of about 3000 xc3x85.
In the fourth step, ST230, the source and drain electrodes are formed by depositing and patterning a metallic material such as Chrome (Cr) or Cr-alloy.
In the fifth step, ST240, a channel region is formed by removing the portion of the doped amorphous silicon (ohmic contact layer) between the source and drain electrodes. In this step, the source and drain electrodes are used as masks. If the portion of the ohmic contact layer between the source and drain electrodes is not removed, serious problems of deteriorated electrical characteristics and lower efficiencies can result in the final TFT.
Generally, the process steps of fabricating the TFT include a step of forming the gate insulation layer, a step of forming the semiconductor layers, and a step of forming the electrodes. The forming of the gate insulation layer and the forming of the semiconductor layers are beneficially performed in the same apparatus.
A CVD (chemical vapor deposition) apparatus is generally used to form the gate insulation layer. A mixture of various gases is injected into the CVD apparatus, which is kept in a vacuum. The gate insulation layer is then formed by chemical reactions of the injected gases. For example, an inert gas (Helium: He), a silicon compound gas (Silane: SiH4), and a nitrogen compound gas (Ammonia: NH3) can be reacted together in the CVD apparatus to form a Silicon Nitride (SiNx) gate insulation layer. However, polymer materials are inevitably created in the CVD apparatus. When forming the insulation layer, those polymer materials can act as particles and alien substances that can induce defects in the TFT. For this reason, the CVD apparatus should always be cleaned. However, there is no perfect way to solve the polymer material problem.
FIG. 4 is an enlarged view of the portion xe2x80x9cAxe2x80x9d of FIG. 2. As shown in FIG. 4, if a particle or alien substance xe2x80x9cPxe2x80x9d is formed on the gate electrode 30 when forming the gate insulting layer 32, the later deposited layers, such as the gate insulation layer 32, the active layer 34 and the ohmic contact layer 36, grow abnormally. Thus, the drain electrode 40 can contact the gate electrode 30 through the abnormal growth portion, i.e., they are short-circuited. This means that the TFT will not function properly.
As shown in FIG. 5, a particle or alien substance xe2x80x9cPxe2x80x9d (a contaminate) can be also form on the gate insulation layer 32 itself. In this case, the active layer 34 can be damaged, causing a deterioration of the TFT.
Moreover, when forming the gate insulation layer, a pinhole (see FIG. 7A) can occur in the gate insulation layer and can grow vertically. This can also cause deterioration of the TFT.
Accordingly, the present invention is directed to a method of manufacturing a thin film transistor (TFT) (as well as the TFT itself) that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
To overcome the problems described above, the principles of the present invention provide a method of manufacturing a thin film transistor (TFT) that includes an effective method of preventing the occurrence of the polymer and the pinhole.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be apparent from that description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve the above objects, the principles of the present invention provide a method of manufacturing a TFT. That method includes providing a substrate, forming a gate electrode on the substrate, forming a first gate insulation layer on the gate electrode and on the gate electrode, and cleaning the first gate insulation layer. After cleaning, the method continues by forming a second gate insulation layer on the first gate insulation layer, sequentially forming a pure semiconductor layer and a doped semiconductor layer on the second gate insulating layer, forming spaced apart source and drain electrodes, and forming a channel region using the source and drain electrodes as a mask.
To clean the first gate insulation layer, the cleaning process is beneficially performed using a brush. The second gate insulation layer is beneficially comprised of the same material as the first gate insulation layer, which is preferably an inorganic material such as SiNx and SiO2. The pure semiconductor layer and the doped semiconductor layer are etched to form an active layer and an ohmic contact layer by using source and drain electrodes as a mask.
To achieve the above objects, the principles of the present invention further provide for a TFT that includes a substrate, a gate electrode on the substrate, a first gate insulation layer on the gate electrode, and a second gate insulation layer on the first gate insulation layer. The second gate insulation layer is beneficially comprised of the same material as the first gate insulation layer and has the thickness that is 50 to 200% that of the first insulation layer. The TFT further includes an active layer on the second insulation layer, an ohmic contact layer on the active layer, and spaced apart source and drain electrodes on the ohmic contact layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.